The continued scaling of integrated circuit technology toward smaller sizes is making system level integration on a chip both possible and desirable. A chip is understood to be a piece of a semiconductor substrate, such as silicon, having thousands to millions of transistors interconnected to perform a specific function. Scaling of semiconductor circuits has had desirable qualities such as being able to provide system circuitry on a single chip, which in turn increases the speed and capability of the system circuit.
In this manner, a system level integration has merged memory-and-logic functions onto a single chip. Dynamic random-access memory ("DRAM") is attractive for such merged system integration because DRAM cells occupy a small area. Thus, DRAM cells potentially allow a large number of memory cells to be integrated with circuit logic functions.
Nevertheless, as transistors are made smaller and faster, delays through the transistor interconnects become more frequent, limiting the speed of the transistor.
Greater transistor scaling has became possible with the emergence of semiconductor technologies--such as silicon-on-insulator ("SOI")--that can be used for merged system integration. An SOI chip is a layered structure having a relatively thin layer of single-crystal silicon either atop an insulating substrate, such as quartz or sapphire, or separated from a bulk silicon substrate by an electrically insulating layer, which has typically been silicon dioxide.
An SOI structure produces devices with smaller junction areas, simpler isolation structures, and steeper subthreshold-voltage slopes than prior bulk devices. Advantages have been the reduction of parasitic capacitances and leakage currents, as well as the ability to use lower supply and threshold voltages without speed loss.
Generally, capacitance is an electrical characteristic that relates to the ability of a structure to store electrical charge. Typically, a comparatively longer time is required to charge the capacitance, as opposed to the actual time required to simply turn a transistor "on" and "off."
With SOI technology, the junction area capacitance of a transistor is reduced, recognizing speed improvements of 200 to 300 percent, and power reduction up to 90 percent relative to bulk silicon counterparts, as well as operation voltages to below 1-volt (Vdd).
In bulk Complementary Metal-Oxide Semiconductor ("CMOS") device fabrication, well structures and other such isolating structures introduce parasitic effects that are harmful to integrated-circuit performance and place constraints on how tightly devices can be packed. In contrast, the isolation layer of the SOI structure permits high- and low-voltage devices to be integrated in close proximity. The isolation layer also can serve as an etch stop in the patterning of silicon waveguides and fabrication of sensor membranes or 3-D structures. Leakage currents induced thermally or by exposure to radiation are reduced, allowing SOI devices to be used in automotive and space electronics.
Because of the new semiconductor structures associated with SOI technology, circuits have been designed to address the structure nuances in such a manner as to further increase the switching speed of a CMOS device, such as a Metal-Oxide Semiconductor Field-Effect Transistor ("MOSFET").
U.S. Pat. No. 5,559,368, issued Sep. 24, 1996, to Hu et al., discloses an integrated circuit for operating at an ultra-low voltage of 0.6 volts or less for circuits implementing large transistors used in clock drivers and large buffers. The structure disclosed is a MOSFET formed in an SOI structure that includes a gate to body connection to provide a forward body-bias for a transistor. The transistor is forward body-biased to enhance the current drive of the device.
Apart from silicon-on-insulator power source concerns, a present need exists to further increase the transition rate for SOI-based devices to further capitalize on the characteristics of SOI technology, as well as to bring an interconnecting node for dynamic-circuits to a known level for predictable circuit behavior. Also, a need exists for these characteristics in a driver circuit coupled to a circuit load.